Power supply voltage for future CMOS VLSI in half and sub micrometer

The trade off between circuit performance and reliability of CMOS devices is theoretically and experimentally examined in detail down to sub micrometer gate length including various effects such as mobility degradation, reliability physics, parasitic capacitances and parasitic resistances. Based upon these cosideration, a new scaling scenario has been proposed to determine power supply voltage for half and lower sub micrometer CMOS devices. The new scaling scheme has been applied to O.6um CMOS device and it has been verified that the power supply voltage can be scaled down maintaining high circuit performance with high reliability.