VDMOS Transistors with improved on-resistance and quasi-saturation characteristics

In this paper VDMOS transistors with lower on-resistance and improved quasi-saturation characteristics, without degrading their breakdown voltage, are experimentally demonstrated and analyzed. The improvement is achieved by raising the doping level in the JFET region by an additional n implant implemented in the standard device fabrication process. Since breakdown normally occurs at the terminating edges, there exists a window where the surface doping density can be increased while the same breakdown voltage is maintained. Two dimensional numerical simulations have been carried out to analyze the devices. Also, to study the effect of the additional surface layer on the on-resistance area product, carrier distribution and breakdown voltage in order to optimize the layer´s resistivity.