• DocumentCode
    3556978
  • Title

    The impact of gate-drain overlapped LDD (GOLD) for deep submicron VLSI´s

  • Author

    Izawa, Ryuichi ; Kure, Tokuo ; Iijima, Shimpei ; Takeda, Eiji

  • Author_Institution
    Hitachi Ltd., Kokubunji, Tokyo, Japan
  • Volume
    33
  • fYear
    1987
  • fDate
    1987
  • Firstpage
    38
  • Lastpage
    41
  • Abstract
    A new device structure GOLD (gate-drain overlapped LDD) is proposed to achieve high reliability and high performance in deep submicron MOSFETs. This device takes advantage of the gate-drain overlap effect. The GOLD device concept is different from that of drain-engineering methods such as the double diffused drain (DDD) and lightly doped drain (LDD). GOLD eliminates the tradeoff between transconductance and breakdown voltage (hot-carrier, drain sustaining). The "overlap effect" of GOLD devices is discussed using device simulation and experimentation. In the fabrication process, GOLD has a novel gate structure using a natural oxide film (5-10 Å) to obtain the overlapped fine structure. The GOLD process is also compatible with conventional LDD processes. As a result, GOLD will be suitable for 0.5-0.3 µm design rule devices at 5 V operation, not 3 V.
  • Keywords
    Dry etching; Fabrication; Gold; Hot carriers; Intrusion detection; Laboratories; Oxidation; Transconductance; Very large scale integration; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1987 International
  • Type

    conf

  • DOI
    10.1109/IEDM.1987.191342
  • Filename
    1487300