DocumentCode
3556999
Title
Three dimensional IC for high performance image signal processor
Author
Nishimura, T. ; Inoue, Y. ; Sugahara, K. ; Kusunoki, S. ; Kumamoto, Y. ; Nakagawa, S. ; Nakaya, M. ; Horiba, Y. ; Akasaka, Y.
Author_Institution
Mitsubishi Electric Corporation, Itami, Japan
Volume
33
fYear
1987
fDate
1987
Firstpage
111
Lastpage
114
Abstract
The three-dimensional (3-D) image processing test IC designed with parallel processing architecture is fabricated. The device consists of 5-by-5 array of photosensors, 2-bit CMOS A-to-D converters, 40 arithmetic logic units (ALU) and shiftregisters arranged in a 3-layer structure. The total operation from photosensor on top layer to ALU on bottom layer is confirmed, and it is also demonstrated the feasibility of very high speed system operation with the implement of parallel processing. This device gives a clear image of the intelligent image processor on one chip as a future application of 3-D ICs.
Keywords
Arithmetic; CMOS logic circuits; Crystallization; Image processing; Logic arrays; Parallel processing; Signal design; Signal processing; Silicon; Three-dimensional integrated circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1987 International
Type
conf
DOI
10.1109/IEDM.1987.191362
Filename
1487320
Link To Document