20V Asymmetric Complementary Power Device Implementation within a 0.25um CMOS Technology for Power Management

Author

Letavic, T. ; Cook, R. ; Brock, R. ; Effing, H. ; Einerhand, R.

Author_Institution

Philips Semicond., Hopewell Junction, NY

fYear

2005

fDate

23-26 May 2005

Firstpage

367

Lastpage

370

Abstract

This paper presents a process flow in which a 20V-class of power devices is added to baseline 0.25mum CMOS technology by forming asymmetric extended-drain device structures in which shallow-trench-isolation (STI) is incorporated within the device unit cell, forming a gate extended-drain dielectric region. The R_sp-BV_ds figure-of-merit is consistent with best-in-class for this device construction (0.16 mOhm cm²/24V), and the isolated high-voltage diode capability make this process cost-effective for implementation of mobile power management circuit topologies, including multiple-output DC-DC converters, battery chargers, linear regulators, audio power amplifiers, and white-light backlighting systems

Keywords

CMOS integrated circuits; isolation technology; power integrated circuits; semiconductor technology; 0.25 micron; CMOS integrated circuits; asymmetric complementary power device; asymmetric extended-drain device structures; gate extended-drain dielectric region; isolated high-voltage diode capability; isolation technology; mobile power management circuit topologies; power integrated circuits; power management application; shallow-trench-isolation; Battery management systems; CMOS process; CMOS technology; Circuit topology; DC-DC power converters; Dielectric devices; Diodes; Energy management; Power system management; Technology management;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 2005. Proceedings. ISPSD '05. The 17th International Symposium on

Conference_Location

Santa Barbara, CA

Print_ISBN

0-7803-8890-9

Type

conf

DOI

10.1109/ISPSD.2005.1488027

Filename

1488027