• DocumentCode
    3558155
  • Title

    Capacitor coupling of GaAs defletion-mode f.e.t.s.

  • Author

    Livingstone, A.W. ; Mellor, P.J.T.

  • Author_Institution
    British Telecom, Research Laboratories, Ipswich, UK
  • Volume
    127
  • Issue
    5
  • fYear
    1980
  • fDate
    10/1/1980 12:00:00 AM
  • Firstpage
    297
  • Lastpage
    300
  • Abstract
    Integration of GaAs depletion mode f.e.t.s requires voltage level shifting between logic stages. Capacitor coupling provides such a shift without the need for additional power rails and with a high tolerance of process parameter variations; being passive, the level shifting consumes no additional power. Data can also be retained dynamically on capacitors in clocked circuits providing exceptionally low power operation. Test circuits have been fabricated which have demonstrated successfully the principles of capacitor coupling. Data from these are being used to design capacitor-coupled logic (c.c.I.) circuits for telecommunication applications. When static operation is essential, capacitor coupling can also be used to enhance the operation of conventionally coupled circuits.
  • Keywords
    III-V semiconductors; Schottky gate field effect transistors; gallium arsenide; logic circuits; GaAs depletion mode FET; III-V semiconductor; capacitor coupling; clocked circuits; voltage level shifting;
  • fLanguage
    English
  • Journal_Title
    Solid-State and Electron Devices, IEE Proceedings I
  • Publisher
    iet
  • Conference_Location
    10/1/1980 12:00:00 AM
  • ISSN
    0143-7100
  • Type

    jour

  • DOI
    10.1049/ip-i-1.1980.0058
  • Filename
    4642526