DocumentCode
3559228
Title
Capacitor-Swapping Cyclic A/D Conversion Techniques With Reduced Mismatch Sensitivity
Author
Kuo, Chun-Hsien ; Kuo, Tai-Haur
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan
Volume
55
Issue
12
fYear
2008
Firstpage
1219
Lastpage
1223
Abstract
This work proposes two capacitor-swapping techniques, random feedback-capacitor interchanging (RFCI) and averaging RFCI (ARFCI) techniques, for cyclic analog-to-digital converters (ADCs) to reduce the harmonic distortion caused by capacitor mismatch without trimming or calibration. The proposed RFCI and ARFCI techniques can be realized by simply rearranging the capacitor connections of the ADCs in different operation cycles. Hence, complicated circuits are not needed. The RFCI technique improves upon the spurious-free dynamic range (SFDR) of conventional ADCs without sacrificing the signal-to-noise-and-distortion ratio (SNDR). The ARFCI technique has better SNDR characteristics but less SFDR improvement than RFCI. With RFCI and ARFCI, the capacitor matching requirement is relaxed for high SFDR and the capacitance can then be reduced to meet the SNDR requirement, reducing the driving capability of the opamps, and thus reducing the total power and area of the ADCs. The prior commutated feedback-capacitor switching (CFCS) technique (see Yu , 1996) has less effect on the SFDR of cyclic ADCs but improves the signal-to-noise ratio (SNR). This work proposes a reconfigurable cyclic ADC architecture that can be easily reconfigured to operate with one of the RFCI, ARFCI, and CFCS techniques by a simple timing control circuit. This reconfigurable topology provides three conversion characteristics with one item of intellectual property (IP), rather than three separate IPs and thus greatly enhances the capabilities of cyclic ADCs.
Keywords
analogue-digital conversion; capacitors; capacitor-swapping cyclic A/D conversion techniques; commutated feedback-capacitor switching technique; cyclic analog-to-digital converters; harmonic distortion; intellectual property; mismatch sensitivity; random feedback-capacitor interchanging; signal-to-noise-and-distortion ratio; spurious-free dynamic range; timing control circuit; Analog-digital conversion; Calibration; Capacitance; Capacitors; Circuit topology; Dynamic range; Harmonic distortion; Intellectual property; Signal to noise ratio; Timing; Analog-to-digital converter (ADC); capacitor mismatch; spurious-free dynamic range (SFDR);
fLanguage
English
Journal_Title
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher
ieee
ISSN
1549-7747
Type
jour
DOI
10.1109/TCSII.2008.2009963
Filename
4698877
Link To Document