An Embedded and Programmable System Based FPGA for Real Time MPEG Stream Buffer Analysis

The MPEG transport stream is an extremely complex structure using interlinked tables and coded identifiers to separate the programs and the elementary streams. Quality management is therefore a complicated issue and the need to identify the degree of coding degradations in terms of coding and/or transmission errors or system failures is becoming an important criterion for the evaluation of the quality of the MPEG streams. A theoretical decoder (T-STD) defines the verification process based on the proper fill level of an MPEG decoder buffers whose size is defined by the standards in order to obtain an evaluation of the MPEG stream quality. This paper describes a new embedded and programmable solution capable of analysing MPEG streams in real time. The proposed hardware architecture provides a real time continuous buffer analysis of the MPEG stream components and is composed of several modules allowing for simultaneous modeling of the various buffers of the T-STD components (video, audio or system). Real time errors flags are generated when the buffers filling level becomes illegal (overflow, empty buffer, transfer delay, etc.). The architecture has been modeled, validated and simulated using the SystemC and VHDL languages in combination with real MPEG DVB-T streams. A VHDL synthesisable model of our architecture allows an implementation on an field-programmable gate array circuit based on Altera APEX20K1000. The hardware implementation of this configurable T-STD allows a data rate of 232 Mbps and requires only 9738 logical cells and 4,7 kB memory.