DocumentCode
3560810
Title
Leveraging Unused Cache Block Words to Reduce Power in CMP Interconnect
Author
Kim, Hyungjun ; Gratz, Paul V.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX, USA
Volume
9
Issue
1
fYear
2010
Firstpage
33
Lastpage
36
Abstract
Power is of paramount importance in modern computer system design. In particular, the cache interconnect in future CMP designs is projected to consume up to half of the system power for cache fills and spills. Despite the power consumed by spills and fills, a significant percentage of each cache line is unused prior to eviction from the cache. If unused cache block words can be identified, this information can be used to improve CMP interconnect power and energy consumption. We propose a new method of CMP interconnect packet composition, leveraging unused data to reduce power. These methods are well suited to interconnection networks with high-bandwidth wires, and do not require expensive multi-ported memory systems. Assuming perfect prediction, our technique achieves an average of 37% savings in total dynamic link power consumption. With our current best prediction mechanism, our techniques reduce dynamic power consumption by 23% on average.
Keywords
cache storage; integrated circuit design; microprocessor chips; power aware computing; CMP interconnect; cache fills; cache interconnect; cache spills; computer system design; energy consumption; power reduction; total dynamic link power consumption; unused cache block words; Cache memories; Interconnection architectures; Low-power design;
fLanguage
English
Journal_Title
Computer Architecture Letters
Publisher
ieee
Conference_Location
6/3/2010 12:00:00 AM
ISSN
1556-6056
Type
jour
DOI
10.1109/L-CA.2010.9
Filename
5476388
Link To Document