DocumentCode
3560894
Title
Multi-processor based CRC computation scheme for high-speed wireless LAN design
Author
Yoon, S.-R. ; Seo, S. ; Huang, M.L. ; Park, S.-C.
Author_Institution
Dept. of Inf. & Commun., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Volume
46
Issue
11
fYear
2010
Firstpage
800
Lastpage
802
Abstract
Presented is a software cyclic redundancy check (CRC) parallel computation scheme for the realisation of a high-speed wireless communication system on a multi-processor design platform. The proposed CRC generation scheme was applied to the IEEE 802.11n WLAN system. As a result, the proposed CRC scheme is capable of meeting tight latency constraint to achieve 144 Mbit/s throughput at a processor frequency less than 200 MHz, when evaluated with register-transfer-level simulation.
Keywords
IEEE standards; cyclic redundancy check codes; multiprocessing systems; parallel algorithms; wireless LAN; CRC generation scheme; CRC parallel computation; IEEE 802.11n WLAN system; high-speed wireless LAN design; high-speed wireless communication system; multiprocessor based CRC computation; multiprocessor design platform; register-transfer-level simulation; software cyclic redundancy check;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el.2010.0145
Filename
5479729
Link To Document