Low-Power CMOS Equalizer Design for 20-Gb/s Systems

Author

Ibrahim, Sameh ; Razavi, Behzad

Author_Institution

Electr. Eng. Dept., Univ. of California, Los Angeles, CA, USA

Volume

46

Issue

6

fYear

2011

fDate

6/1/2011 12:00:00 AM

Firstpage

1321

Lastpage

1336

Abstract

The power consumption of wireline circuits has become increasingly more critical as the pin count and data rate rise. This paper describes a power scaling methodology and a new half-rate speculative architecture for decision-feedback equalizers (DFEs) to relax the speed-power trade-offs. Designed in 90-nm CMOS technology, a 20-Gb/s prototype consisting of a linear equalizer and a one-tap DFE compensates for the loss of an 18-in FR4 trace while drawing 40 mW from a 1-V supply.

Keywords

CMOS integrated circuits; decision feedback equalisers; low-power electronics; CMOS technology; bit rate 20 Gbit/s; data rate; decision feedback equalizer; half-rate speculative architecture; linear equalizer; low-power CMOS equalizer design; pin count; power consumption; power scaling methodology; size 90 nm; wireline circuit; CMOS integrated circuits; Clocks; Decision feedback equalizers; Latches; Noise; Sensitivity; Bit error rate; CML latch; decision-feedback equalizers; high-speed equalizers; latch offset; latch sensitivity; unrolled DFE;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

Conference_Location

5/5/2011 12:00:00 AM

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2011.2134450

Filename

5763723