• DocumentCode
    35615
  • Title

    NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs

  • Author

    Meng-Kai Hsu ; Yi-Fang Chen ; Chau-Chin Huang ; Sheng Chou ; Tzu-Hen Lin ; Tung-Chieh Chen ; Yao-Wen Chang

  • Author_Institution
    Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • Volume
    33
  • Issue
    12
  • fYear
    2014
  • fDate
    Dec. 2014
  • Firstpage
    1914
  • Lastpage
    1927
  • Abstract
    A wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements. Therefore, it is desirable to develop an effective routability-driven placer for modern mixed-size designs employing hierarchical methodologies for faster turnaround time. In this paper, we propose a novel routability-driven analytical placement algorithm for hierarchical mixed-size circuit designs. This paper presents a novel design hierarchy identification technique to effectively identify design hierarchies and guide placement for better wirelength and routability. The proposed algorithm optimizes routability from four major aspects: 1) narrow channel handling; 2) pin density; 3) routing overflow optimization; and 4) net congestion optimization. Routability-driven legalization and detailed placement are also proposed to further optimize routing congestion. Compared with the participating teams for the 2012 ICCAD Design Hierarchy Aware Routability-driven Placement Contest, our placer can achieve the best quality (both the average overflow and wirelength) and the best overall score (by additionally considering running time).
  • Keywords
    circuit optimisation; integrated circuit layout; network routing; NTUplace4h; hierarchical methodologies; hierarchical mixed-size circuit designs; hierarchy identification technique; modern mixed-size designs; narrow channel handling; net congestion optimization; pin density; routability-driven analytical placement algorithm; routability-driven placement algorithm; routability-driven placer; routing congestion; routing overflow optimization; routing-congested placements; wirelength-driven placer; Algorithm design and analysis; Circuit synthesis; Design methodology; Optimization; Routing; Global routing; layouts; physical design; placement;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2014.2360453
  • Filename
    6951861