Modeling of SSN noise using time domain impedance analysis and PSO optimization Algorithm

In the design of high complexity systems, the significance of signal integrity plays a vital role and in turn depends on the occurrence of different noises such as crosstalk noise, reflection noise, switching noises and active periodic noise. These noises are more in the design of IC, PCB layout design and multilayered PCB. However the impact of Simultaneous Switching Noise (SSN) noises in a IC with coupling of power delivery system becomes an important issue and this papers addresses the optimization of signal integrity by placing optimal values of decoupling capacitor to reduce (SSN) using PSO optimization algorithm. This is implemented by modeling of PDN, package and IC. The experimental analysis validate the result and the reduction of SSN for different capacitor by adjusting the time domain impedance function rather than frequency domain and the magnitude of SSN is reduced to 0.0125v for adjusting the time period and 0.01v for adjusting the inductance.