DocumentCode
3565156
Title
0.026µm2 high performance Embedded DRAM in 22nm technology for server and SOC applications
Author
Pei, C. ; Wang, G. ; Aquilino, M. ; Arnold, N. ; Chandra, B. ; Chang, W. ; Chen, X. ; Davies, W. ; Hawkins, K. ; Jaeger, D. ; Johnson, J.B. ; Kwon, O.-J. ; Krishnasamy, R. ; Kong, W. ; Liu, J. ; Li, X. ; Messenger, B. ; Nelson, E. ; Nummy, K. ; Onishi, K.
Author_Institution
IBM Semicond. R&D Center, Hopewell Junction, NY, USA
fYear
2014
Abstract
This paper presents the industry´s smallest Embedded Dynamic Random Access Memory (eDRAM) implemented in IBM´s 22nm SOI technology. The bit cell area of 0.026μm2 achieves ~60% scaling over the previous generation with deep trench (DT) capacitance optimized for performance and retention requirements. We report, for the first time, the asymmetric embedded stressor, cavity implant, through gate implant, and substrate n-band innovations to maintain aggressive cell scaling for the 22nm eDRAM technology.
Keywords
DRAM chips; silicon-on-insulator; system-on-chip; DT capacitance; IBM SOI technology technology; SOC application; aggressive cell scaling; asymmetric embedded stressor; bit cell area; cavity implant; deep trench capacitance; eDRAM; embedded dynamic random access memory; high-performance embedded DRAM; retention requirement; server application; size 22 nm; substrate n-band innovation; through gate implant; Cavity resonators; Computer architecture; Field effect transistors; Implants; Junctions; Logic gates; Microprocessors;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2014 IEEE International
Type
conf
DOI
10.1109/IEDM.2014.7047083
Filename
7047083
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