Low power transmitter/receiver circuit for over 25Gbps operation

Recent communication for cloud computing strongly requires an order of magnitude wider bandwidth than current one, such as over 28Gbps in SerDes and Interiaken protocols. So the IO transmitter and receiver becomes to one of key issues. In generally, those high bandwidth IO systems consume relative high power due to relate with fCV^2 by CMOS transistor and parasitic capacitances. Additional problem is that the transmitter needs to drive long wiring of mother board or plug-in board. Some adaptive equalizer and timing adjust circuits must be implemented in the IO circuit that also requires power consumption. Our research has been aimed to save to quarter times power of current ones even in over 28Gbps band width operation. The key was for balanced concurrent design from chip design to board design and open termination circuit system. These will be mentioned here.