MRC training vs. board defect

Using debug experiments to prove the concept, we correlated failures in the MRC training log with board defects and, in doing so, established a new usage model for MRC board defect capture flow/methodology. We helped customers identify board defect locations by conducting PCB cross-sectional analysis at those locations. This resulted in PCB vendor process improvement by avoiding random board defects. Our MRC training analysis for board defect capturing on DDR nets can apply to any DDR relative design, especially those designs with DRAM chips device down. This methodology/flow fits into the validation process during both production and post-production. It helps customers avoid the high cost of product callback and penalty. The main difficulty is in convincing PCB vendors to do PCB cross-sectional analysis themselves to identify defects in their manufacturing process.