A low power, wide dynamic range multigain signal processor for the SNAP CCD

Author

Walder, J.-P. ; Chao, G. ; Genat, J.F. ; Karcher, A. ; Krieger, B. ; Kurz, S. ; Steckert, J. ; von der Lippe, H.

Author_Institution

Lawrence Berkeley Nat. Lab., Berkeley Heights, NJ, USA

Volume

1

fYear

2003

Firstpage

1

Abstract

A four-channel custom chip designed for reading out the CCDs of the SNAP satellite visible imager is presented. Each channel consists of a single-ended to differential converter followed by a correlated double sampler and a novel multi slope integrator. The output signal is differentially brought out of the chip by an output buffer. This circuit is designed to operate at room temperature for test purpose and at 140K, which will be the operating temperature. The readout speed is 100kHz. The 16-bit dynamic range is covered using 3 gains each with a 12 bit signal to noise ratio. The prototype chip, implemented in a 0.25 μm CMOS technology, has a measured readout noise of 7μV rms at 100kHz readout speed, a measured non-linearity of ±0.025% and a power consumption of 6.5mW.

Keywords

CCD image sensors; CMOS integrated circuits; analogue-digital conversion; signal processing equipment; 0.25 micron; 100 kHz; 140 K; 16 bit; 6.5 mW; CMOS technology; SNAP CCD; Super Nova/-Acceleration Probe; correlated double sampler; four-channel custom chip; low power wide dynamic range multigain signal processor; multi slope integrator; output signal; readout speed; signal to noise ratio; single-ended to differential converter; CMOS technology; Charge coupled devices; Circuit testing; Dynamic range; Noise measurement; Power measurement; Semiconductor device measurement; Signal processing; Temperature; Velocity measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Nuclear Science Symposium Conference Record, 2003 IEEE

ISSN

1082-3654

Print_ISBN

0-7803-8257-9

Type

conf

DOI

10.1109/NSSMIC.2003.1351986

Filename

1351986