XCC-a tool for designing parameterizable IP cores in VHDL

As time to market and the ability to design a system on a chip become the prime determinant of the economic viability of new products, FPGAs are being used in applications calling for thousands or even millions of gates. Critical to implementing such systems quickly is the existence of intellectual property cores on lines similar to the large libraries provided by ASIC vendors. Here at XILINX, we are in the process of defining a methodology for creating and distributing IP cores targeted to XILINX FPGAs. We describe a tool for creating such IP cores in VHDL, the lingua franca of PLD based system designers. This tool is able so convert IP cores specified in structural (and, perhaps, parametric) VHDL into a form that can be distributed in a reasonably secure format. This tool makes it possible for third-party IP developers to create cores targeted to XILINX FPGAs merely by specifying the core in VHDL. Such a core may contain special implementation directives aimed at achieving better mapping into a target FPGA. In the final analysis, the core generation process is greatly simplified and accelerated.