Design and simulation of on-chip circuits for parallel characterization of ultrascaled transistors for BTI reliability

A novel on-chip test circuit architecture to perform BTI characterization of single devices using the Measure-Stress-Measure (MSM) method is designed and simulations were performed to confirm that the design is fully functional. Characterization throughput was maximized using pipelining. A `place-and-check´ algorithm was developed to generate optimized pipelining of individual device measurements. The novel pipelining methodology was corroborated with real measurements, in accordance with the generated pipelining sequence and proposed circuit architecture. The results are shown to be consistent with the data obtained from conventional measurement methods and an improvement of 82% was achieved in total BTI characterization time of 4096 devices.