A digital baseband for low power FSK based receiver in 65 nm CMOS

Author

Sherazi, S. M. Yasser ; Sjoland, Henrik ; Nilsson, Peter

Author_Institution

Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden

fYear

2014

Firstpage

159

Lastpage

162

Abstract

The design of a digital baseband for a low power wireless receiver in 65 nm CMOS is presented. It consists of decimation filtering, matched filters for data detection, and preamble based synchronization. The circuit was designed using low threshold devices in both low power (LP-LVT) and general-purpose (GP-LVT) domains. The fabricated circuits were functionally verified, and silicon measurements show a minimum energy dissipation of around 454 pJ and 708 pJ per output bit at a rate of 500kbit/s for the LP-LVT and GP-LVT implementations, respectively.

Keywords

CMOS integrated circuits; frequency shift keying; integrated circuit design; low-power electronics; matched filters; radio receivers; GP-LVT; LP-LVT; circuit design; data detection; decimation filtering; digital baseband; energy dissipation; general-purpose-LVT; low power FSK-based receiver; low power wireless receiver; low threshold devices; matched filters; preamble-based synchronization; silicon measurements; size 65 nm; Baseband; Bit error rate; CMOS integrated circuits; Energy dissipation; Frequency shift keying; Receivers; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on

Type

conf

DOI

10.1109/ICECS.2014.7049946

Filename

7049946