Design of a lifting wavelet processor for one dimensional signal

Author

Kuzume, Koichi ; Niijima, Koichi ; Takano, Shigeru

Author_Institution

Yuge Nat. Coll. of Technol., Ehime, Japan

Volume

2

fYear

2004

Abstract

This paper presents the realization of a lifting wavelet processor for signal detection on a field programmable gate array (FPGA) device. This processor implements an algorithm for detecting target portions from a signal using an integer type Haar lifting wavelet transform (IHLWT), which we proposed. The VLSI can be designed using a small amount of circuitry, consisting of only 6 multipliers and 9 adders with a pipeline architecture. The VLSI is designed using hardware description language (HDL) and is simulated on the FPGA in practice. The test scenarios covering several kinds of electrocardiogram (ECG) signals are examined thoroughly.

Keywords

Haar transforms; VLSI; field programmable gate arrays; hardware description languages; integrated circuit design; microprocessor chips; pipeline processing; signal detection; wavelet transforms; 1D signal; ECG signals; FPGA device; VLSI design; adders; electrocardiogram signals; field programmable gate array; hardware description language; integer type Haar lifting wavelet transform; lifting wavelet processor design; multipliers; pipeline architecture; signal detection; target portion detection; Adders; Circuits; Field programmable gate arrays; Hardware design languages; Pipelines; Signal design; Signal detection; Signal processing; Very large scale integration; Wavelet transforms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on

Print_ISBN

0-7803-8346-X

Type

conf

DOI

10.1109/MWSCAS.2004.1354183

Filename

1354183