EPD time delay as WSix stack down gate etching in DPS+ chamber

Device makers want to make higher density chips as devices shrink, especially WSix polystack down is one of the key issues. However, EPD (end point detection) time delay was happened in DPS+ poly chamber which is a barrier to achieve device shrink because EPD time delay killed test pattern and next generation device. To investigate the EPD time delay, a test was done with patterned wafers. This experiment was carried out combined with OES (optical emission spectroscopy) and SEM (scanning electron microscopy). OES was used to find corrected wavelength in WSix stack down gate etching. SEM was used to confirm WSix gate profile and gate oxide damage. Through the experiment, a new wavelength (252 nm) line of plasma is selected for DPS+ chamber to call correct EPD in WSix stack down gate etching for current device and next generation device.