Two level 2-DDWT convolution structure for high speed operation using Daubehies wavelet

The Discrete Wavelet Transform (DWT) has a huge number of applications in science and engineering technology. It is used for signal coding, to represent a discrete signal in a more redundant form, often as a preconditioning for data compression. Practical applications can also be found in signal processing, digital communications and many others. There are several techniques available for DWT like orthogonal, bi-orthogonal, HAAR, Dual-Tree Complex Wavelet Transform, and Newland transform. A multiplier-less based architecture on algebraic integer representation for computing the Daubechies6-tap wavelet transform is used for two level 2D-DWT as wavelet filters in image processing. This architecture improves on previous designs in a way that it minimizes the number of parallel 2-input adder circuits. In this paper the design is implemented for a two-level 2-D decomposition using a Xilinx Virtex-6 xc6vcx75t-2-ff484 field programmable gate array (FPGA) device operating at up to a maximum clock frequency of 344/168 MHz.