Integration of electroless copper for seed repair

Author

Witt, C. ; Frank, A. ; Webb, E. ; Reid, J. ; Pfeifer, K.

Author_Institution

Int. Sematech, Austin, TX, USA

fYear

2002

fDate

6/24/1905 12:00:00 AM

Firstpage

259

Lastpage

261

Abstract

Electroless copper deposition was studied at International Sematech to show the feasibility of enhancement or repair of physical vapor deposition (PVD) copper seeds in a damascene metallization sequence. Void free copper fill was achieved on single damascene features that meet the requirements of the International Technology Roadmap for Semiconductors (ITRS) for interconnect for the 100 nm and 70 nm technology nodes. Copper films with seed repair were subjected to film stress and gas desorption measurements. In addition, electroless seed repair was incorporated in high aspect ratio dual damascene structures.

Keywords

copper; electroless deposition; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; internal stresses; maintenance engineering; sputtered coatings; 100 nm; 70 nm; Cu; International Technology Roadmap for Semiconductors; PVD copper seeds; copper films; damascene metallization sequence; electroless copper deposition integration; electroless seed repair; film stress measurements; gas desorption measurements; high aspect ratio dual damascene structures; interconnect technology nodes; physical vapor deposition copper seeds; seed repair; single damascene features; void free copper fill; Atherosclerosis; Chemical vapor deposition; Conductors; Copper; Damascene integration; Dielectric substrates; Etching; Metallization; Silicon compounds; Stress measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International

Print_ISBN

0-7803-7216-6

Type

conf

DOI

10.1109/IITC.2002.1014951

Filename

1014951