Impact of Polysilicon Depletion Effect on Circuit Performance for 0.35μ CMOS Technology

The impact of reduced polysilicon doping concentration Np on circuit performance is analyzed using a new polysilicon depletion model. SPICE simulations of inverter chains with different loadings predict that higher circuit delays are expected as Np is reduced. The performance degradation gets compounded when the gate oxide thickness tox is reduced, and/or substrate concentration Nb is increased. For a given tox and non-degenerate value of Np, lowering the channel length helps to reduce the polydepletion effect and hence circuit performance degradation. However, reducing the power supply, for low power operation, enhances the polydepletion effect.