• DocumentCode
    3573143
  • Title

    In-Situ Doped P+ Polysilicon as a MOS Gate Material

  • Author

    Dantu, S.V. ; Tarr, N.G. ; Peters, C.J.

  • Author_Institution
    Department of Electronics, Carleton University, Ottawa, Ontario, Canada K1S 5B6
  • fYear
    1994
  • Firstpage
    373
  • Lastpage
    376
  • Abstract
    The effect of rapid thermal anneal cycles typical of those required for source/drain implant activation on flatband voltage, interface state density, and dielectric strength in MOS capacitors with heavily in-situ boron doped polysilicon gates over thin thermal oxide is studied. Anneal cycles of up to 1050°C, 10 s should be acceptable for use of in-situ doped p+ gates in a CMOS process.
  • Keywords
    Boron; CMOS technology; Capacitance-voltage characteristics; Channel bank filters; Doping; Implants; MOS capacitors; MOSFETs; Rapid thermal annealing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Device Research Conference, 1994. ESSDERC '94. 24th European
  • Print_ISBN
    863321579
  • Type

    conf

  • Filename
    5435739
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3573143