A Novel Fault Diagnosis in Reversible Logic Circuit

Reversible circuits have widespread applications in quantum computing, low power circuit design, nanotechnology, cryptography etc. The paper addresses the fault diagnosis problem in reversible logic circuit for missing gate fault model. The key idea of this paper is to extract the fault signature for each of the missing gate faults in a reversible circuit. Fault signatures are generated using the successive tree form of Multi-Input Signature Analyzer (MISA). Fault diagnosis is performed by verifying the signature of the circuit under test. The proposed method rapidly identifies the fault locations and the experimental results for benchmark circuits exhibit the efficiency of the technique.