Techniques for improving timing convergence of advanced microprocessors

The wire capacitance models that are used in synthesis tools are typically based on the number of fanouts. These wire capacitance models can be misleading when compared to real wiring. This discrepancy can cause synthesis tools to optimize incorrectly, causing severe problems with chip-level timing convergence. Designs may take longer than expected and designers may work on timing paths that are not critical, thus increasing the design cycle time. In submicron designs, it is crucial to improve the timing convergence between the synthesis and the physical design. This paper describes several practical approaches used in the timing convergence of an advanced PowerPC microprocessor. The impact of each approach is evaluated on the timing and the size of the microprocessor