A 13-mW 0.22-mm2 continuous-time Delta-Sigma ADC with 68-dB dynamic range in 10-MHz bandwidth

This paper presents a 3^rd-order continuous-time (CT) Delta-Sigma modulator (DSM) for broadband digital transceivers. In this design, a low-cost Proportional-Integrating (PI) element Excess Loop Delay (ELD) compensation method is adopted to mitigate the influence of ELD. Meanwhile, to avoid the compensation zero and loop filter coefficients variation due to process variation, an on-chip automatic RC constant tuning block is used to trim the RC constant. The proposed DSM is fabricated in a 0.13 um 1P6M CMOS technology and occupies an active area of 0.22 mm². It achieves 68 dB dynamic range (DR), 66 dB peak signal to noise plus distortion ratio (SNDR) in 10 MHz bandwidth under 500MHz sampling frequency and dissipates 13 mW power under 1.5 V power supply.