Double gate FinFET master slave Flip-Flop design for low power application

In this paper, we are presenting various analyses on master slave D Flip-Flop which is designed using FinFET. Master Slave Flip-Flop is advanced version of Flip-flops. To make Master Slave Flip-Flop Normal Flip-Flop is followed by Clocked S-R Flip-Flop. According to Moore´s law the no. of transistor in a meticulous chip area is two times in every 18 months. This announcement gives new age of VLSI meadow. If we want to increase the no. of component in chip area so we diminish the size of component. Appling this quality in chip component, the size of transistor reduced. As we scale down the device parameter after a certain rule, the short channel effects like leakage power, surface scattering, velocity saturations, takes place. Fin-FET is a superior device to eliminate or decrease above mentioned problems. We evaluate the various parameters like temperature effect to the total power, total power consumption, average DC power, calculation etc. For calculation of these results we are use cadence tools. After simulating the circuit we get values of Average DC power which is 160nW, Instantaneous Transient Power Consumption is 65.20nW, Delay is 30nS.