DocumentCode
358095
Title
Register binding for predicated execution in DSP applications
Author
Zhao, Q. ; van Eijk, C.A.J. ; Pinto, C. A Alba ; Jess, J.A.G.
Author_Institution
Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
fYear
2000
fDate
2000
Firstpage
113
Lastpage
118
Abstract
Predicated execution is an efficient mechanism to avoid conditional constructs in application programs. In this paper we describe how an existing method for register binding can be extended to support predicated execution. The method exploits the combination of register constraints, resource and timing constraints and models the overlap of value lifetimes in a conflict graph. In our extension, mutually exclusive values are identified and are used for reconstructing the conflict graph. Register binding for predicated execution in case of software pipelining is also addressed in this paper. Experiments in the Facts environment show that the register pressure is greatly reduced with this technique
Keywords
constraint handling; digital signal processing chips; high level synthesis; parallel processing; probabilistic logic; processor scheduling; resource allocation; DSP applications; Facts environment; conflict graph; predicated execution; register binding; resource constraints; software pipelining; timing constraints; Control system synthesis; Design automation; Digital signal processing; High level synthesis; Pipeline processing; Registers; Resource management; Scheduling algorithm; Timing; Tree graphs;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits and Systems Design, 2000. Proceedings. 13th Symposium on
Conference_Location
Manaus
Print_ISBN
0-7695-0843-X
Type
conf
DOI
10.1109/SBCCI.2000.876017
Filename
876017
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