Yield maximization of TiO2>/sub> memristor-based memory arrays

The missing fourth passive circuit element, the memristor, attracted a great attention when HP labs developed the first real memristor device in 2008. The memristor manufacturing is facing various challenges due to the difficulty to control its process variation, as it is fabricated at nano-scale geometry´s size. Process variation result in deviating the actual electrical behavior of memristors from the desired values. This deviation results in reducing the yield especially in the memristor-based memory design. Therefore, it is very important to understand and characterize the impact of process variation on memristor performance and yield and attempt to maximize the yield of the memristor-based memory arrays.