Efficient implementation of FIR filters using bit-level optimized carry-save additions

A widely used technique to implement high-speed fixed-coefficients FIR filters in VLSI circuits is to use carry-save additions (CSA) to defer the time-consuming carry-propagations. This paper shows that by exploiting the unequal wordlength of the partial products generated by the fixed-coefficients, significant savings can be achieved by optimizing the carry-save representation at the bit-level. The key in our proposed technique is to allow for more than two signals per bit position, so that we gain flexibility in the bit-level implementation of CSA arrays. We have applied our algorithms to the optimization of high-speed digital FIR filters and have achieved 15% to 30% savings (weighted cost) in the overall filter implementation array in comparison to the standard carry-save implementation.