Embracing the FPGA Challenge for Processor Design Verification

Functional verification of modern general purpose superscalar microprocessor design and validating the processor for all possible combinations of state transitions is an enormous challenge. A typical processor design goes through multiple stages of simulation, verification and evaluation before it is taped out for physical implementation. As the processor design and verification moves from one stage to the next, the cost of identifying and fixing design bugs increases significantly. FPGA verification provides a cost effective, scalable and rich environment for hunting deeper design bugs as compared to emulators and simulators, as it allows large number of verification cycles running at much closer to real time operation speeds but on the other hand, it does not offer same level of visibility and control over the design as compared to simulation and emulation environments. This lack of design visibility and control in FPGA introduces new challenges for the verification tool developers, design and debug engineers. This paper describes the challenges faced by the processor verification tools developers and debug engineers for verifying a processor design on FPGA implementation and few techniques that were successfully used at ARM to mitigate some of these challenges.