Mulit-core architecture for real-time and energy-efficient bearing fault diagnosis

Author

Myeongsu Kang ; Inkyu Jeong ; Jong-Myon Kim

Author_Institution

Univ. of Ulsan, Ulsan, South Korea

fYear

2014

Firstpage

72

Lastpage

73

Abstract

This paper proposes a high-performance single-instruction, multiple-data (SIMD)-based multi-core architecture including 64 processing elements operating at 50 MHz in a Xilinx Virtex-7 field programmable gate array (FPGA) device to support online bearing fault diagnosis. The experimental results indicate that the proposed multi-core approach executes 1,293× faster than a high-performance Texas Instrument (TI) TMS320C6748 digital signal processor (DSP) by exploiting the massive parallelism inherent in the bearing fault diagnosis algorithm. In addition, the multi-core approach outperforms the equivalent sequential approach that runs on the TI DSP by substantially reducing the energy consumption.

Keywords

fault diagnosis; field programmable gate arrays; machine bearings; mechanical engineering computing; parallel architectures; power aware computing; FPGA; SIMD-based multicore architecture; Xilinx Virtex-7 field programmable gate array; energy consumption reduction; energy-efficient bearing fault diagnosis; frequency 50 MHz; high-performance single-instruction-based multicore architecture; mulitcore architecture; multiple-data-based multicore architecture; online bearing fault diagnosis; Decoding; Discrete wavelet transforms; Service-oriented architecture; FPGA; SIMD; multi-core architecture; online bearing fault diagnosis;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2014 International

Type

conf

DOI

10.1109/ISOCC.2014.7087601

Filename

7087601