• DocumentCode
    3593717
  • Title

    A Load Balancing Scheme for Two-Stage Switches Maintaining Packet Sequence

  • Author

    Lee, Hyoung-Il ; Lee, Bhum-Cheol ; Seo, Seung-Woo

  • Author_Institution
    Electronic and Electrical Examination Bureau, Korean Intellectual Property Office, Daejeon, Korea 302-701. Email: hi@ieee.org
  • Volume
    1
  • fYear
    2006
  • fDate
    6/1/2006 12:00:00 AM
  • Firstpage
    293
  • Lastpage
    298
  • Abstract
    In this paper, we propose a novel load-balancing scheme for two-stage switches which does not disturb the sequence of packets. The proposed scheme uses chamber queues(CQs) in front of the second crossbar fabric as well as VOQs in front of the first crossbar. A chamber queue is composed of N banks each of which can store only one packet destined for each output. The two crossbar fabrics in the proposed switch are configured by a deterministic sequence of N connection patterns as in other two-stage switches. In a time slot, the proposed switch transfers packets from non-empty VOQs to the corresponding empty banks of CQs via the first crossbar, and the packets from CQs are switched to their destinations via the second crossbar. While the proposed scheme is very simple, it can achieve 100% throughput under not only uniform but also non-uniform traffic. Moreover, the simulation results show that the average delay of packets in the proposed two-stage switch is lower than that in the original two-stage switch.
  • Keywords
    Communication switching; Computer architecture; Delay; Fabrics; Field-flow fractionation; Load management; Packet switching; Processor scheduling; Switches; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communications, 2006. ICC '06. IEEE International Conference on
  • ISSN
    8164-9547
  • Print_ISBN
    1-4244-0355-3
  • Electronic_ISBN
    8164-9547
  • Type

    conf

  • DOI
    10.1109/ICC.2006.254743
  • Filename
    4024133