Split accumulator with phase modulation for high speed low power direct digital synthesizers

A new split accumulator architecture to be used in direct digital frequency synthesizer (DDS) systems is presented in this paper. This new design takes into consideration that only part of the accumulator output is used to address the sine wave mapping. The most significant bits of the accumulator drive the mapping block and need to be updated on every sampling clock, while the least significant bits are not visible to the rest of the design and can be updated less frequently. Also the phase modulation adder is moved to the front of the accumulator. Benefits of the proposed architecture are fewer constraints in implementation, reduced power consumption of 40% (estimation) compared to standard approaches, and less area with no degradation in terms of spurious-free dynamic range (SFDR) performance.