Modeling of substrate contacts in TSV-based 3D ICs

This paper proposes closed-form expressions of parasitic parameters in a silicon substrate that consider substrate contacts. In general bulk CMOS technologies, the standard cells with bulk (substrate and well) contacts or tap cells for bulk contacts are used in physical layout designs. As tap cell placement methods, there are dense random placements and sparse regular placements in cell rows vertically. We call the former the fine-grained substrate contacts and the latter the coarse-grained ones. First, their structures are modeled for simplification, and then the equivalent circuit model is presented. Next, closed-form expressions of parasitic parameters for TSV-to-TSVs and TSV-to-contacts are proposed. Finally, validity of the proposed method is discussed. The proposed expressions agree with 3D electromagnetic field solvers with reasonable accuracy. When an enormous amount of TSVs are placed regularly, designers can extract parasitic parameters quickly.