Modeling of partially cracked and void hole defected through silicon via interconnections

Author

Gerakis, Vasileios ; Liolios, Alexandros ; Hatzopoulos, Alkis

Author_Institution

Dept. of Electr. & Comput. Eng., Aristotle Univ. of Thessaloniki, Thessaloniki, Greece

fYear

2014

Firstpage

1

Lastpage

6

Abstract

Lumped analytical electrical models for partially cracked and void hole defected TSVs are proposed in this paper. Accurately modeling defects may enhance the test methodology and could be vital to improve the quality of TSV-based 3D-ICs. These models were verified by simulations using a commercial 3D resistance, capacitance and inductance extraction tool. The presented simulation results are in close agreement with the proposed analytical expressions.

Keywords

cracks; integrated circuit interconnections; integrated circuit modelling; integrated circuit reliability; three-dimensional integrated circuits; voids (solid); 3D extraction tool; TSV-based 3D-IC; capacitance; inductance; lumped analytical electrical model; modeling defect; partially cracked defect; resistance; through silicon via interconnection; void hole defect; Capacitance; Fitting; Integrated circuit modeling; Resistance; Silicon; Solid modeling; Three-dimensional displays; 3D ICs; TSV; fault modeling; partial crack; void hole defect;

fLanguage

English

Publisher

ieee

Conference_Titel

Design of Circuits and Integrated Circuits (DCIS), 2014 Conference on

Type

conf

DOI

10.1109/DCIS.2014.7154073

Filename

7154073