Pipelining of GaAs dynamic logic circuits

Dynamic latch circuits that allow pipelining of dynamic GaAs logic gates are presented. The latches offer fast operation and good tolerance to skew between the two complementary clock signals required for pipelining. Two 4-bit prescaler/counters, which use dynamic domino and dynamic CVSL gates, were implemented in a 1 μm process to demonstrate that the latches can be used to pipeline practical circuit designs. The prescaler/counters, which can be set to count from anywhere between 2 and 16, operated at approximately 800 MHz while dissipating 60 and 82 mW of power for the domino and CVSL versions, respectively