VLSI Implementation of Low Power Multiple Single Input Change (MSIC) Test Pattern Generation for BIST Scheme

The main challenging areas in VLSI design are performance, cost, testing, area, reliability and power. The demand for portable computing devices and communication system are increasing rapidly. The power dissipation during test mode is much more than in normal mode. Hence it is important to optimize power during testing. BIST is a Design for Testability (DFT) technique, because it makes the electrical testing of a chip easier, faster, more efficient, and less costly. Hence the low power Multiple Single Input Change (MSIC) test patterns are generated for BIST based schemes. The characteristics of these multiple single input change patterns are minimum transition, uniform distribution and uniqueness of patterns. A reconfigurable Johnson counter, XOR array and a seed generator are used for generating test patterns. The seed generator is a linear feedback shift register. A single seed or multiple seeds can be used which will affect the number of patterns generated. Since the patterns are of low transitions, the power dissipation during test mode can be reduced. Here the generated patterns are given to different scan chains. To reduce the hardware overhead, delay and power consumption an accumulator based circuit can be used. The generated patterns are applied to the s344 benchmark circuit for fault injection and fault detection. The coding is done in VHDL and is simulated in XILINX ISE simulator.