Integrated memory/logic architecture for image processing

Typical low-level image processing tasks require thousands of operations per pixel for each input image. The structure of the tasks suggests employing an array of processing elements, one per pixel, sharing instructions issued by a single controller. To build pixel-parallel image processing hardware for microcomputer systems, large processing element arrays must be produced at low cost. Integrated circuit designers have had tremendous success creating dense and inexpensive semiconductor memories. They handcraft circuits to perform essential functions using very little silicon area, then replicate the circuits to form large memory arrays. This paper shows how the same technique may be applied to create a dense integrated processing element array