• DocumentCode
    3600006
  • Title

    Path delay testing: variable-clock versus rated-clock

  • Author

    Majumder, Subhashis ; Agrawal, Vishwani D. ; Bushnell, Michael L.

  • Author_Institution
    ECE Dept., Rutgers Univ., Piscataway, NJ, USA
  • fYear
    1998
  • Firstpage
    470
  • Lastpage
    475
  • Abstract
    There are two methods for applying path delay tests to a sequential circuit. We show that all path delay faults that can affect the rated-clock operation of the circuit are testable by the variable-clock method. Also, all path delay faults that are untestable by the variable-clock method are, in fact, untestable by the rated-clock method. However, some faults tested by the variable-clock method may be incapable of affecting the rated-clock operation. Our study is based on a finite-state machine model in which fault-free transitions are shown by green arcs. Faulty transitions are shown by red arcs. A test traverses successive arcs until a faulty output occurs. A variable-clock test can exercise more flexibility in selecting from green and red arcs. It can cover all functional paths, but may find only a proper subset of untestable paths. Our analysis assumes a delay fault, consisting of either a singly-testable path or multiply-testable paths, and hence corresponds to non-robust detection
  • Keywords
    finite state machines; logic testing; sequential circuits; colored edge model; faulty transition; finite state machine; green arc; path delay testing; rated-clock method; red arc; sequential circuit; variable-clock method; Circuit faults; Circuit testing; Clocks; Combinational circuits; Delay; Frequency; Logic testing; Sequential circuits; Synchronization; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on
  • ISSN
    1063-9667
  • Print_ISBN
    0-8186-8224-8
  • Type

    conf

  • DOI
    10.1109/ICVD.1998.646651
  • Filename
    646651