• DocumentCode
    3600942
  • Title

    A Multiphase DLL With a Novel Fast-Locking Fine-Code Time-to-Digital Converter

  • Author

    Dandan Zhang ; Hai-Gang Yang ; Wenrui Zhu ; Wei Li ; Zhihong Huang ; Lin Li ; Tianyi Li

  • Author_Institution
    Inst. of Electron., Beijing, China
  • Volume
    23
  • Issue
    11
  • fYear
    2015
  • Firstpage
    2680
  • Lastpage
    2684
  • Abstract
    This brief presents a fast-locking multiphase closed-loop delay-locked loop (DLL). The proposed DLL employs a novel rapid-tracking time-to-digital converter that spends only two clock cycles to generate fine codes. This greatly reduces the fine-locking time and hence the total locking time that goes down to eight input reference clock cycles, shortened by 80%-95% compared with previously reported closed-loop architectures. Fabricated in a 130-nm technology, the proposed DLL operates at 80-450 MHz. In addition, the measured rms and peak-to-peak jitters at 180 MHz are 2.3 and 10 ps, respectively.
  • Keywords
    delay lock loops; jitter; program compilers; time-digital conversion; closed-loop architecture; delay-locked loop; fast-locking fine-code time-to-digital converter; fine code generation; frequency 180 MHz; frequency 80 MHz to 450 MHz; line-locking time; multiphase DLL; peak-to-peak jitter; rapid-tracking time-to-digital converter; reference clock cycle; size 130 nm; Clocks; Delay lines; Delays; Frequency measurement; Inverters; Jitter; Tuning; Delay-locked loop (DLL); fast locking; multiphase; time-to-digital converter (TDC); time-to-digital converter (TDC).;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2014.2369460
  • Filename
    6980134