• DocumentCode
    3606890
  • Title

    3D-ProWiz: An Energy-Efficient and Optically-Interfaced 3D DRAM Architecture with Reduced Data Access Overhead

  • Author

    Thakkar, Ishan G. ; Pasricha, Sudeep

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Colorado State Univ., Fort Collins, CO, USA
  • Volume
    1
  • Issue
    3
  • fYear
    2015
  • Firstpage
    168
  • Lastpage
    184
  • Abstract
    This paper introduces 3D-ProWiz, which is a high-bandwidth, energy-efficient, optically-interfaced 3D DRAM architecture with fine grained data organization and activation. 3D-ProWiz integrates sub-bank level 3D partitioning of the data array to enable fine-grained activation and greater memory parallelism. A novel method of routing the internal memory bus to individual subarrays using TSVs and fanout buffers enables 3D-ProWiz to use smaller dimension subarrays without significant area overhead. The use of TSVs at subarray-level granularity eliminates the need to use slow and power hungry global lines, which in turn reduces the random access latency and activation-precharge energy. 3D-ProWiz yields the best latency and energy consumption values per access among other well-known 3D DRAM architectures. Experimental results with PARSEC benchmarks indicate that 3D-ProWiz achieves 41.9 percent reduction in average latency, 52 percent reduction in average power, and 80.6 percent reduction in energy-delay product (EDP) on average over DRAM architectures from prior work.
  • Keywords
    DRAM chips; buffer circuits; memory architecture; network routing; power aware computing; system buses; three-dimensional integrated circuits; 3D-ProWiz; EDP reduction; PARSEC benchmarks; TSV; activation-precharge energy reduction; data access overhead reduction; data array; energy-delay product reduction; fanout buffers; fine-grained data activation; fine-grained data organization; high-bandwidth-energy-efficient-optically-interfaced 3D DRAM architecture; internal memory bus routing; memory parallelism; random access latency reduction; subarray-level granularity; subbank level 3D partitioning integration; Bandwidth; Parallel processing; Random access memory; Three-dimensional displays; Through-silicon vias; DRAM; Fine-grained activation; energy-effi-ciency; energy-efficiency; fanout buffers;
  • fLanguage
    English
  • Journal_Title
    Multi-Scale Computing Systems, IEEE Transactions on
  • Publisher
    ieee
  • Type

    jour

  • DOI
    10.1109/TMSCS.2015.2481425
  • Filename
    7274744