An In-Depth Analysis of Ring Oscillators: Exploiting Their Configurable Duty-Cycle

Ring oscillators are used in many applications, but for all of them the system output is a clock signal with a 50% duty cycle. Our work sets the analytical basis for understanding and designing a ring oscillator whose outputs are clock signals with fully-configurable duty cycles different from 50%. We present two models in order to vary the output duty cycle with reduced area overhead: the first model is based on the layout design, focusing on the transistor sizing of each inverter gate; and the second model establishes a relation between the output duty cycle and different bias voltage schemes. These models are validated by simulation with a 40 nm commercial technology. The simulations include the impact of variability and the characterization of the oscillator phase noise. We also discuss the utilization of our new approach in many different applications for heterogeneous environments.