SEU and SET of 65 Bulk CMOS Flip-flops and Their Implications for RHBD

Author

Yuanfu Zhao ; Liang Wang ; Suge Yue ; Dan Wang ; Xinyuan Zhao ; Yongshu Sun ; Dongqiang Li ; Fuqing Wang ; Xiaoqian Yang ; Hongchao Zheng ; Jianhua Ma ; Long Fan

Author_Institution

Beijing Microelectron. Technol. Inst., Beijing, China

Volume

62

Issue

6

fYear

2015

Firstpage

2666

Lastpage

2672

Abstract

Two 65 nm bulk CMOS test chips, each containing several different types of flip-flop chains, are designed and tested. Heavy ion results are given and analyzed across ion LET and in proposed time domain. The single event upset (SEU) and single event transient (SET) performance of various DFFs are compared and discussed, concluding several practical implications for radiation hardening by design (RHBD). The effectiveness of redundant delay filter (RDF) on mitigating SETs is proven by experiment for the first time.

Keywords

CMOS logic circuits; delay filters; flip-flops; integrated circuit design; integrated circuit reliability; integrated circuit testing; radiation hardening (electronics); CMOS flip-flops; CMOS test chips; RDF; RHBD; SET; SEU; heavy ion; ion LET; radiation hardening by design; redundant delay filter; single event transient; single event upset; size 65 nm; Flip-flops; Radiation hardening (electronics); Single event transients; Single event upsets; Time-domain analysis; Dual interlocked cell (DICE); flip-flop; radiation hardening by design (RHBD); redundant delay filter (RDF); single event transient (SET); single event upset (SEU); soft error; time domain analysis;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2015.2490552

Filename

7348836