Pushing the scaling limits of embedded non-volatile memories with high-K materials

In this paper, two alternative cell concepts to overcome these issues were discussed: conventional floating gate cells with high-K inter-poly dielectrics (IPD) and nitride trapping devices with high-K materials. In both concepts, the reduced equivalent oxide thickness (EOT) of the high-K layers helps reducing VPE, whereas the low leakage current ensures a good data retention. In this work, only hafnium based high-K materials were used: hafnium oxide (HfO₂) and nitrided hafnium silicate (HfSiON), both deposited by MOCVD. The choice for these materials was based on their expected availability in the sub-45nm CMOS nodes