SPERT: a VLIW/SIMD neuro-microprocessor

SPERT (synthetic perceptron testbed) is a fully programmable single chip microprocessor designed for efficient execution of artificial neural network algorithms. The first implementation will be in a 1.2 mu m CMOS technology with a peak 50 MHz clock rate. A prototype system is being designed to occupy a double SBus slot within a sun Sparcstation. With fast external SRAM, SPERT will sustain over 300*10/sup 6/ connections per second during pattern classification, and around 100*10/sup 6/ connection updates per second while running the error backpropagation training algorithm. This represents a speedup of around two orders of magnitude over a Sparcstation2 for algorithms of interest. An earlier system, the ring array processor (RAP), used commercial DSP chips. Compared with a RAP multiprocessor of similar performance, SPERT represents over an order of magnitude reduction in cost for problems where fixed-point arithmetics is satisfactory.