• DocumentCode
    3623407
  • Title

    A supercomputer for neural computation

  • Author

    K. Asanovic;J. Beck;J. Feldman;N. Morgan;J. Wawrzynek

  • Author_Institution
    Int. Comput. Sci. Inst., California Univ., Berkeley, CA, USA
  • Volume
    1
  • fYear
    1994
  • Firstpage
    5
  • Abstract
    The requirement to train large neural networks quickly has prompted the design of a new massively parallel supercomputer using custom VLSI. This design features 128 processing nodes, communicating over a mesh network connected directly to the processor chip. Studies show peak performance in the range of 160 billion arithmetic operations per second. This paper presents the case for custom hardware that combines neural network-specific features with a general programmable machine architecture, and briefly describes the design in progress.
  • Keywords
    "Supercomputers","Neural networks","Very large scale integration","Computer architecture","Delay","Communication system control","Speech","Bandwidth","Mesh networks","Arithmetic"
  • Publisher
    ieee
  • Conference_Titel
    Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on
  • Print_ISBN
    0-7803-1901-X
  • Type

    conf

  • DOI
    10.1109/ICNN.1994.374129
  • Filename
    374129